During the conventional buried contact process, misalignment of a polysilicon pattern can either damage the silicon substrate or cause discontinuity between a buried contact N+region and a source/drain N+region. To illustrate these problems, a representative example of the prior art technology for a buried contact process is shown in FIG. 1A through FIG. 3C.
In FIG. 1A, a silicon substrate 10 is covered by a thin silicon oxide layer 12 which functions as gate dielectric. A thin layer of polysilicon 14 is deposited on the thin silicon oxide layer 12.
In FIG. 1B, a photoresist mask 16 is formed on the thin polysilicon layer 14 to define the buried contact pattern.
In FIG. 1C, the exposed portion of the thin polysilicon layer 14 and the portion of the thin silicon oxide layer 12 that is underneath the exposed portion of the thin polysilicon layer 14 are anisotropically etched. The buried contact hole 18 is thereby, formed.
In FIG. 1D, an ion implantation is performed through the buried contact hole 18 to form a buried contact N+region 20.
In FIG. 1E, the photoresist mask 16 is removed and a layer of polysilicon 22 is deposited on the surface. The polysilicon layer 22 is heavily doped with an N-type dopant such as phosphorous to create a low electrical resistance film.
In FIG. 1F, a second photoresist mask 24 is formed on the polysilicon layer 22 to define a pattern in the polysilicon layer 22.
In FIG. 1G, the portions of the polysilicon layers 22, 14 exposed by the second photoresist mask 24 are anisotropically etched.
In FIG. 1H, the portions of the thin silicon oxide layer 12 that are now exposed by etching the polysilicon are anisotropically etched too.
In FIG. 1I, the second photoresist mask 24 is removed and an ion implantation is performed through the openings 27 to form N+regions 26, 28 that function as source/drain.
There cannot be any discontinuity between the source/drain region 26 and the buried contact 20. Therefore, alignment of the second photoresist mask 24 is very important.
FIG. 2A shows a "right misalign" of the photoresist mask 24 during patterning of the polysilicon layers 22, 14. In particular, the mask openings 30 are too far to the right. In FIG. 2B, an anisotropic etching is performed and the exposed polysilicon etched away. In FIG. 2C, an anisotropic etching is performed and the exposed portions of the thin silicon oxide layer 12 are etched away. In FIG. 2D, the photoresist mask 24 is removed and an ion implantation is performed through the openings 30 to form source/drain N+regions 26', 28'. The buried contact N+region 20 and source/drain N+region 26' are separated by a discontinuity 38 because of the right misalign in patterning polysilicon layers 22, 14.
FIG. 3A shows a "left misalign" during patterning of the polysilicon layers 22, 14. In particular, mask openings 40 are too far to the left. In FIG. 3B, an anisotropic etching is performed through the openings 40 and the exposed portions of the polysilicon layers 22, 14 are etched away. Due to the similarity in etching rate of the polysilicon layers 12, 14 and the silicon substrate 10, etching damage occurs in the substrate 10. The damage arose because the opening 40 is too far to the left so that some of the substrate was exposed (i.e., not covered by the oxide 12). This damage may be deep enough to form a trench 42. In FIG. 3C, an anisotropic etching is performed through the openings 40 and exposed portions of the thin silicon oxide layer 12 are etched away. In FIG. 3D, the photoresist mask 24 is removed and an ion implantation is performed to form source/drain N+regions 26", 28". It should be noted that an N+region 29 is formed under the trench 42. This N+region 29 is not necessary for device operation. The buried contact N+region 20 and source/drain N+region 26" are isolated by the trench 42 because of the left misalign in patterning the polysilicon layers 22, 14.
The following are prior art references related to the formation of a buried contact.
Stanly Wolf, "Silicon Process for the VLSI Era", Lattice Press, Sunset Beach, Calif., 1986.
Calvin T. Gabriel, James P. McVittie, "How Plasma Etching Damages Thin Gate Oxides", Solid State Technology, June 1992, p. 81-87.
U.S. Pat. No. 5,162,259
U.S. Pat. No. 5,126,285
U.S. Pat. No. 5,326,713
U.S. Pat. No. 5,145,797
In view of the foregoing, it is an object of the present invention to provide an improved process for making a buried contact, the improved process having an increased alignment tolerance.